[755-1] problems with VDD and GND

[Konstantinos Dovrolis <dovrolis@nova32.cs.wisc.edu>]

Folks

There is a problem, as several of you noticed, with the
LVS checks on the top-level layout, and specifically
with the VDD and GND ports. The problem was that I didn't
write some necessary parts of the process at the 8th
tutorial.. the fixes are easy, fortunately.

First, note that for the SDL or full-custom generated
layout blocks, you need to have a VDD and a GND pair of
pins at the logic symbol that corresponds to the layout
block. I have updated the corresponding image at the
8th tutorial to illustrate this point. At the top-level
schematic, then, you should connect these VDD and GND 
pins to the corresponding VDD and GND power supplies
that you can find at the GENLIB (after renaming the
vcc and vee supplies, and giving the right voltage values). 
Again, see the 8th tutorial's top-level schematic,
if this paragraph sounds too complicated.

Note that you don't need to connect VDD and GND pins
at the std-cell logic symbols, because the connection
of std-cells with the power supplies is done automatically.

Another point that causes problems: make sure at each
layout block that is generated automatically that the VDD and
GND ports are of type "POWER" and of direction "IN" (not OUT!).
You can easily see the properties of all layout ports, by
selecting a layout block and then selecting the menu:
Report->Ports->All.
If they power ports have the wrong direction, you can select
each of them and then select: Object->Change->Port to edit
their properties.

In summary, if you do have the above problem:

1. you need
to add the VDD and GND pins at the logic symbols that correspond
to SDL or full-custom layout blocks.

2. you need to connect these pins at the top-level schematic
with the corresponding power supplies.

3. you need to make sure that the layout VDD and GND ports are
of type POWER-IN, and if they are not, to edit them.

C.