[755-1] Clock generation/distribution

[Konstantinos Dovrolis <dovrolis@cs.wisc.edu>]

The project specifications had a major omission (which 
is totally my fault). We did not specify how are you going
to generate the clock. So, most groups I suppose they
drive all the clock inputs in their system with the externally
provided clock, which in the simulations it has *infinite*
driving capability. This is certainly not what would happen
in practice.

Of course this is too late to change the requirements, so
you can ignore this problem. If however you do have some time
and you want to add an extra special feature in your project
(which will of course make a difference in the evaluation)
you can design a clock distribution network for your project.

If you decide to do so, note:

1. the external clock input should only feed-in a minimum-size
inverter. It is the output of this inverter that drives the
clock buffering and distribution network.

2. you have to carefully design the clock buffering network. This
usually consists of a chain of inverters, of gradually increasing
widths. The theoretical optimal stage ratio is around 2.7, but 
I have seen papers with improved models that were suggesting a ratio
of 5 or more.

3. you have to carefully design the clock distribution network.
In other words, where are you going to place the above buffers, 
and how are you going to interconnect them? With a 2-metal layer
technology this is not always easy, but you can try to have a tree
or an H-structure (discussed in the paper about HP-PA8000 that we
saw in class).

C.