[755-1] Project-related

[Konstantinos Dovrolis <dovrolis@cs.wisc.edu>]

Folks

We are less than a week from the project's deadline. 
We will announce the details for the demos early
in the next week. It will probably be on Friday,
May 13, though, so please let me know if you have
a conflict on that day.

Some general comments on what you should focus on:

1. Detailed functional testing, based on Quicksim
simulations. Do the results agree with your what
your functional simulator gives?

2. LVS checks for each block of your layout, including
the top-level block. This is important, since checking the layout
with Accusim simulations is much more painful.

3. You should have a good idea of what is the maximum
clock frequency that your layout can work at, i.e., to
know the critical-path scenarios and delays. This is
the point that you will need to use Accusim simulations
on the extracted netlist. 

4. Of course, there should be no design-rule violations
in your full-custom or SDL blocks.

Note that although the assignment grading was "completion-driven"
(i.e., if you do the work you get full-credit), the grading
of the project will emphasize on the effort that you have
put for advanced performance, compact layout, additional
features etc.

Again, details on what will the demo include, and what should
be written in the report will be announced sometime early
next week.

Good luck with your project!

C.