[755-1] Backannotation vs Netlist-Extraction

[Konstantinos Dovrolis <dovrolis@cs.wisc.edu>]

Folks,

This message refers to the issue of post-layout simulations 
with Accusim. I will also add this discussion to Tutorial-6. 

So far, we saw how we can do such simulations using Netlist 
Extraction (see Tutorial-6).
The main steps of that procedure were:
1. Create the layout in IC Station.
2. Extract the netlist, including the "lumped" parasitics.
3. Create a symbol in Design Architect that is mapped
   to the netlist (using the properties ELEMENT, and MODEL).
4. Create a schematic in Design Architect that includes
   the previous symbol (plus other possible symbols),
   and that forms the circuit that is going to be simulated
   in Accusim.
5. Create an Accusim viewpoint for this schematic using DVE.
6. Simulate this viewpoint with Accusim.

The above procedure is quite lengthy and error-prone.
There is, though, an alternative for doing post-layout verification
using Accusim, that is based on backannotation.  You may want to use either
extraction or backannotation, or both. In general, the extraction method is 
more reliable and accurate, since the simulation is based on the actual
extracted information from the layout. Additionally,
the netlist contains some additional geometrical information
about the devices (source and drain areas), that is not included
in the backannotation. Also, the backannotation does not include 
coupling capacitances, but only capacitances between each 
node and GND. On the other hand, backannotation-based simulations
are easier to make.

Specifically, suppose that you have
a Design Architect transistor-based schematic (e.g., for
your 19-bit carry-select adder). Also, you have created an
SDL viewpoint for this schematic (using the sdl_prep) script.
Suppose now that you are done with the creation of the 
layout (using full-custom or SDL), and that you have run DRC 
and LVS successfully. Now, select IC Extract (M) and then
Lumped, as you would normally do for extracting a netlist.
In the form that appears, however, do not select "Netlist",
but "Specify Schematic Source".
As the "Source Name", type the path of the SDl viewpoint
that you created with sdl_prep. For example, type something
like: 
	$PROJ_PARTS_youraccount/MyDesigns/CSA_19bit/sdl
Then, select "Setup LVS", and do whatever you would normally
do when running an LVS check (select GND as the ground name,
and specify that the tool should not try to recognize gates).

Also, select "Yes" in the "Backannotate" option, and
then specify a "BA Name" for the backannotation (e.g., CSA_19bit.ba).
Finally, as the "Lumped Capacitance" property name, select 
"cap_net", as opposed to "icap_net".

Click OK, and the backannotation will be created and attached to
your SDL viewpoint. If you want to see the actual capacitance
values, open the viewpoint with DVE. For each wire that you select,
you can view (and edit) the parasitic capacitance by editing
the property "cap net" of the wire. Note that reported values
are in picoFarads.

Now that you have the backannotated SDL viewpoint, you can simulate
it with Accusim as you know from tutorial-5.
Two important points, though:
1. As the Model Library use "$MGC_HEP/technology/accusim/fets.mod",
   as opposed to "$PROJ_PARTS_cs755/fets.mod".
2. In your transistor schematic and layout, use GND as the ground
   name (as opposed to VSS). If you already have used VSS, you can
   simply change it to GND (it is just a property name).

Let me know if you have any problems with this procedure. 

C.